The present invention relates to static random-access memory (SRAM) and more particularly to a wordline stability assist scheme to improve the tradeoff between cell stability due to read disturb and writeability.
The popular 6T SRAM cell, which utilizes six transistors to store a memory bit and is the industry workhorse today, has always been a challenge for scaling from one technology to the next. Designing the memory for an acceptable yield for cell stability and writeability to the cell has been a challenge under today's constraints of low voltage operation, very high process variation, large amount of memory on die, and area efficiency (or cost per bit). Various techniques have been proposed in the prior art, each having a tradeoff in one way or the other. Some approaches have even moved away from the 6T cell at a high cost of area efficiency.